EECS 370, Introduction to Computer Organization
Pipelined CPU and Cache Simulator
A cycle-accurate 5-stage pipelined LC-2K CPU simulator in C, with a configurable write-back cache.
What I built
- Built a cycle-accurate 5-stage pipelined LC-2K CPU simulator in C, covering fetch through write-back with explicit pipeline registers.
- Implemented forwarding paths, load-use stall control, and branch-not-taken prediction to minimize pipeline stalls under RAW and control hazards.
- Added a configurable write-back cache with LRU replacement, tracking hit and miss stats and modeling memory hierarchy behavior.
- Wrote 20+ targeted assembly test cases to catch pipeline and cache edge-case bugs, meeting mutation-testing thresholds against buggy reference implementations.